Field-programmable gate array
"FPGA" redirects here.
It is not to be confused with Flip-chip pin grid array.
FPGAs contain an array of programmable logic blocks, and a hierarchy of "reconfigurable interconnects" that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations.
FPGAs have a remarkable role in the embedded system development due to capability to start system software (SW) development simultaneously with hardware (HW), enable system performance simulations at a very early phase of the development, and allow various system partitioning (SW and HW) trials and iterations before final freezing of the system architecture.
Contemporary field-programmable gate arrays (FPGAs) have large resources of logic gates and RAM blocks to implement complex digital computations.
As FPGA designs employ very fast I/O rates and bidirectional data buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time.
Floor planning enables resource allocation within FPGAs to meet these time constraints.
FPGAs can be used to implement any logical function that an ASIC can perform.
The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.
Some FPGAs have analog features in addition to digital functions.
The most common analog feature is a programmable slew rate on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly.
Also common are quartz-crystal oscillators, on-chip resistance-capacitance oscillators, and phase-locked loops with embedded voltage-controlled oscillators used for clock generation and management and for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery.
A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip (SoC).
Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.
PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable).
However, programmable logic was hard-wired between logic gates.
Altera was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the die to erase the EPROM cells that held the device configuration.
In December 2015, Intel acquired Altera.
The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.
The XC2064 had 64 configurable logic blocks (CLBs), with two three-input lookup tables (LUTs).
More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention.
In 1987, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates.
Casselman was successful and a patent related to the system was issued in 1992.
Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market share.
By 1993, Actel (now Microsemi) was serving about 18 percent of the market.
By 2013, Altera (31 percent), Actel (10 percent) and Xilinx (36 percent) together represented approximately 77 percent of the FPGA market.
The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production.
By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.
Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the data centers that operate their Bing search engine), due to the performance per watt advantage FPGAs deliver.
Additionally, new, non-FPGA architectures are beginning to emerge.
Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.
- 1987: 9,000 gates, Xilinx
- 1992: 600,000, Naval Surface Warfare Department
- Early 2000s: Millions
- 2013: 50 Million, Xilinx
- 1985: First commercial FPGA : Xilinx XC2064
- 1987: $14 million
- ≈1993: >$385 million
- 2005: $1.9 billion
- 2010 estimates: $2.75 billion
- 2013: $5.4 billion
- 2020 estimate: $9.8 billion
A design start is a new custom design for implementation on an FPGA.
- 2005: 80,000
- 2008: 90,000
Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts.
An older study showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.
More recently, FPGAs such as the Xilinx Virtex-7 or the Altera Stratix 5 have come to rival corresponding ASIC and ASSP ("Application-specific standard part", such as a standalone USB interface chip) solutions by providing significantly reduced power usage, increased speed, lower materials cost, minimal implementation real-estate, and increased possibilities for re-configuration 'on-the-fly'.
A design that included 6 to 10 ASICs can now be achieved using only one FPGA.
Vendors can also take a middle road via FPGA prototyping: developing their prototype hardware on FPGAs, but manufacture their final version as an ASIC so that it can no longer be modified after the design has been committed.
This is often also the case with new processor designs.
Xilinx claimed that several market and technology dynamics are changing the ASIC/FPGA paradigm as of February 2009:
- Integrated circuit development costs were rising aggressively
- ASIC complexity has lengthened development time
- R&D resources and headcount were decreasing
- Revenue losses for slow time-to-market were increasing
- Financial constraints in a poor economy were driving low-cost technologies.
These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts (see § History).
Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.
Complex Programmable Logic Devices (CPLD)
As a result, CPLDs are less flexible, but have the advantage of more predictable timing delays and a higher logic-to-interconnect ratio.
FPGA architectures, on the other hand, are dominated by interconnect.
This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex electronic design automation (EDA) software.
In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs.
When a design requires simple instant-on (logic is already configured at power-up) CPLDs are generally preferred.
For most other applications FPGAs are generally preferred.
Sometimes both CPLDs and FPGAs are used in a single system design.
Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design.
FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors, concerning hardware security.
FPGAs' flexibility makes malicious modifications during fabrication a lower risk.
Previously, for many FPGAs, the design bitstream was exposed while the FPGA loads it from external memory (typically on every power-on).
FPGAs that store their configuration internally in nonvolatile flash memory, such as Microsemi's ProAsic 3 or Lattice's XP2 programmable devices, do not expose the bitstream and do not need encryption.
With its Stratix 10 FPGAs and SoCs, Altera introduced a Secure Device Manager and physically uncloneable functions to provide high levels of protection against physical attacks.
In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that FPGAs can be vulnerable to hostile intent.
They discovered a critical backdoor vulnerability had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and access keys, accessing unencrypted bitstream, modifying low-level silicon features, and extracting configuration data.
See also: Hardware acceleration
An FPGA can be used to solve any problem which is computable.
As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full systems on chips (SoCs).
Particularly with the introduction of dedicated multipliers into FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of digital signal processor hardware (DSPs) began to incorporate FPGAs instead.
Another trend in the use of FPGAs is hardware acceleration, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a generic processor.
The search engine Bing is noted for adopting FPGA acceleration for its search algorithm in 2014.
Traditionally, FPGAs have been reserved for specific vertical applications where the volume of production is small.
For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC.
As of 2017, new cost and performance dynamics have broadened the range of viable applications.
Main article: Logic block
Generally, all the routing channels have the same width (number of wires).
Multiple I/O pads may fit into the height of one row or the width of one column in the array.
An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic.
Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of lookup tables (LUTs) and I/Os can be routed.
This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.
As of 2018, network-on-chip architectures for routing and interconnection are being developed.
In general, a logic block consists of a few logical cells (called ALM, LE, slice etc.).
The LUTs are in this figure split into two 3-input LUTs.
In normal mode those are combined into a 4-input LUT through the left multiplexer (mux).
In arithmetic mode, their outputs are fed to the adder.
The selection of mode is programmed into the middle MUX.
Modern FPGA families expand upon the above capabilities to include higher level functionality fixed in silicon.
Having these common functions embedded in the circuit reduces the area required and gives those functions increased speed compared to building them from logical primitives.
Higher-end FPGAs can contain high speed multi-gigabit transceivers and hard IP cores such as processor cores, Ethernet medium access control units, PCI/PCI Express controllers, and external memory controllers.
These cores exist alongside the programmable fabric, but they are built out of transistors instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic.
The multi-gigabit transceivers also contain high performance analog input and output circuitry along with high-speed serializers and deserializers, components which cannot be built out of LUTs.
Higher-level physical layer (PHY) functionality such as line coding may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
Most of the circuitry built inside of an FPGA is synchronous circuitry that requires a clock signal.
FPGAs contain dedicated global and regional routing networks for clock and reset so they can be delivered with minimal skew.
Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate clock domains.
These clock signals can be generated locally by an oscillator or they can be recovered from a high speed serial data stream.
FPGAs generally contain block RAMs that are capable of working as dual port RAMs with different clocks, aiding in the construction of building FIFOs and dual port buffers that connect differing clock domains.
Following the introduction of its 28 nm 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.
Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon interposer – a single piece of silicon that carries passive interconnect.
The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers.
An FPGA built in this way is called a heterogeneous FPGA.
Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other die/technologies to the FPGA using Intel's embedded multi-die interconnect bridge (EMIB) technology.
Design and programming
The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand.
However, schematic entry can allow for easier visualization of a design and its component modules.
The netlist can then be fit to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software.
Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA.
However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages.
To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process.
These predefined circuits are commonly called intellectual property (IP) cores, and are available from FPGA vendors and third-party IP suppliers.
They are rarely free, and typically released under proprietary licenses.
Other predefined circuits are available from developer communities such as OpenCores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources.
Such designs are known as "open-source hardware."
In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process.
Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate-level description where simulation is repeated to confirm the synthesis proceeded without errors.
More recently, OpenCL (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide.
OpenCL allows programmers to develop code in the C programming language and target FPGA functions as OpenCL kernels using OpenCL constructs.
Basic process technology types
- SRAM – based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS. Currently in use. Notably, flash memory or EEPROM devices may often load contents into internal SRAM that controls routing and logic.
- Fuse – One-time programmable. Bipolar. Obsolete.
- Antifuse – One-time programmable. CMOS.
- PROM – Programmable Read-Only Memory technology. One-time programmable because of plastic packaging. Obsolete.
- EPROM – Erasable Programmable Read-Only Memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.
- EEPROM – Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS.
- Flash – Flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
At that time, they controlled nearly 90 percent of the market.
Both Xilinx and Altera provide proprietary electronic design automation software for Windows and Linux (ISE/Vivado and Quartus) which enables engineers to design, analyze, simulate, and synthesize (compile) their designs.
Other manufacturers include:
- Microsemi (previously Actel), producing antifuse, flash-based, mixed-signal FPGAs; acquired by Microchip in 2018
- Atmel, a second source of some Altera-compatible devices; also FPSLIC mentioned above; acquired by Microchip in 2016
- Lattice Semiconductor, which manufactures low-power SRAM-based FPGAs featuring integrated configuration flash, instant-on and live reconfiguration
- SiliconBlue Technologies, which provides extremely low power SRAM-based FPGAs with optional integrated nonvolatile configuration memory; acquired by Lattice in 2011
- QuickLogic, which manufactures Ultra Low Power Sensor Hubs, extremely low powered, low density SRAM-based FPGAs, with display bridges MIPI & RGB inputs, MIPI, RGB and LVDS outputs
- Achronix, manufacturing SRAM based FPGAS with 1.5 GHz fabric speed
On March 24, 2015, Tabula officially shut down.
On June 1, 2015, Intel announced it would acquire Altera for approximately $16.7 billion and completed the acquisition on December 30, 2015.
On October 27, 2020, AMD announced it would acquire Xilinx.
- FPGA Mezzanine Card
- FPGA prototyping
- List of HDL simulators
- List of Xilinx FPGAs
- Verilog and SystemVerilog hardware description languages
- VHDL, Very High Speed Integrated Circuit hardware description language
- Hardware acceleration for an overview of computing based primarily in hardware
Credits to the contents of this page go to the authors of the corresponding Wikipedia page: en.wikipedia.org/wiki/Field-programmable gate array.