Field-programmable gate array

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"FPGA" redirects here. Field-programmable gate array_sentence_0

It is not to be confused with Flip-chip pin grid array. Field-programmable gate array_sentence_1

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence the term "field-programmable". Field-programmable gate array_sentence_2

The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Field-programmable gate array_sentence_3

Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. Field-programmable gate array_sentence_4

FPGAs contain an array of programmable logic blocks, and a hierarchy of "reconfigurable interconnects" that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations. Field-programmable gate array_sentence_5

Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. Field-programmable gate array_sentence_6

In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Field-programmable gate array_sentence_7

Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurable computing as performed in computer software. Field-programmable gate array_sentence_8

FPGAs have a remarkable role in the embedded system development due to capability to start system software (SW) development simultaneously with hardware (HW), enable system performance simulations at a very early phase of the development, and allow various system partitioning (SW and HW) trials and iterations before final freezing of the system architecture. Field-programmable gate array_sentence_9

Technical design Field-programmable gate array_section_0

Contemporary field-programmable gate arrays (FPGAs) have large resources of logic gates and RAM blocks to implement complex digital computations. Field-programmable gate array_sentence_10

As FPGA designs employ very fast I/O rates and bidirectional data buses, it becomes a challenge to verify correct timing of valid data within setup time and hold time. Field-programmable gate array_sentence_11

Floor planning enables resource allocation within FPGAs to meet these time constraints. Field-programmable gate array_sentence_12

FPGAs can be used to implement any logical function that an ASIC can perform. Field-programmable gate array_sentence_13

The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications. Field-programmable gate array_sentence_14

Some FPGAs have analog features in addition to digital functions. Field-programmable gate array_sentence_15

The most common analog feature is a programmable slew rate on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates on heavily loaded pins on high-speed channels that would otherwise run too slowly. Field-programmable gate array_sentence_16

Also common are quartz-crystal oscillators, on-chip resistance-capacitance oscillators, and phase-locked loops with embedded voltage-controlled oscillators used for clock generation and management and for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Field-programmable gate array_sentence_17

Fairly common are differential comparators on input pins designed to be connected to differential signaling channels. Field-programmable gate array_sentence_18

A few "mixed signal FPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip (SoC). Field-programmable gate array_sentence_19

Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric. Field-programmable gate array_sentence_20

History Field-programmable gate array_section_1

The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). Field-programmable gate array_sentence_21

PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). Field-programmable gate array_sentence_22

However, programmable logic was hard-wired between logic gates. Field-programmable gate array_sentence_23

Altera was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the die to erase the EPROM cells that held the device configuration. Field-programmable gate array_sentence_24

In December 2015, Intel acquired Altera. Field-programmable gate array_sentence_25

Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially viable field-programmable gate array in 1985 – the XC2064. Field-programmable gate array_sentence_26

The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market. Field-programmable gate array_sentence_27

The XC2064 had 64 configurable logic blocks (CLBs), with two three-input lookup tables (LUTs). Field-programmable gate array_sentence_28

More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention. Field-programmable gate array_sentence_29

In 1987, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Field-programmable gate array_sentence_30

Casselman was successful and a patent related to the system was issued in 1992. Field-programmable gate array_sentence_31

Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market share. Field-programmable gate array_sentence_32

By 1993, Actel (now Microsemi) was serving about 18 percent of the market. Field-programmable gate array_sentence_33

By 2013, Altera (31 percent), Actel (10 percent) and Xilinx (36 percent) together represented approximately 77 percent of the FPGA market. Field-programmable gate array_sentence_34

The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production. Field-programmable gate array_sentence_35

In the early 1990s, FPGAs were primarily used in telecommunications and networking. Field-programmable gate array_sentence_36

By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications. Field-programmable gate array_sentence_37

Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the data centers that operate their Bing search engine), due to the performance per watt advantage FPGAs deliver. Field-programmable gate array_sentence_38

Microsoft began using FPGAs to accelerate Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their Azure cloud computing platform. Field-programmable gate array_sentence_39

Integration Field-programmable gate array_section_2

Soft Core Field-programmable gate array_section_3

An alternate approach to using hard-macro processors is to make use of soft processor IP cores that are implemented within the FPGA logic. Field-programmable gate array_sentence_40

Nios II, MicroBlaze and Mico32 are examples of popular softcore processors. Field-programmable gate array_sentence_41

Many modern FPGAs are programmed at "run time", which has led to the idea of reconfigurable computing or reconfigurable systems – CPUs that reconfigure themselves to suit the task at hand. Field-programmable gate array_sentence_42

Additionally, new, non-FPGA architectures are beginning to emerge. Field-programmable gate array_sentence_43

Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip. Field-programmable gate array_sentence_44

Timelines Field-programmable gate array_section_4

Gates Field-programmable gate array_section_5

Field-programmable gate array_unordered_list_0

  • 1987: 9,000 gates, XilinxField-programmable gate array_item_0_0
  • 1992: 600,000, Naval Surface Warfare DepartmentField-programmable gate array_item_0_1
  • Early 2000s: MillionsField-programmable gate array_item_0_2
  • 2013: 50 Million, XilinxField-programmable gate array_item_0_3

Market size Field-programmable gate array_section_6

Field-programmable gate array_unordered_list_1

  • 1985: First commercial FPGA : Xilinx XC2064Field-programmable gate array_item_1_4
  • 1987: $14 millionField-programmable gate array_item_1_5
  • ≈1993: >$385 millionField-programmable gate array_item_1_6
  • 2005: $1.9 billionField-programmable gate array_item_1_7
  • 2010 estimates: $2.75 billionField-programmable gate array_item_1_8
  • 2013: $5.4 billionField-programmable gate array_item_1_9
  • 2020 estimate: $9.8 billionField-programmable gate array_item_1_10

Design starts Field-programmable gate array_section_7

A design start is a new custom design for implementation on an FPGA. Field-programmable gate array_sentence_45

Field-programmable gate array_unordered_list_2

  • 2005: 80,000Field-programmable gate array_item_2_11
  • 2008: 90,000Field-programmable gate array_item_2_12

Comparisons Field-programmable gate array_section_8

To ASICs Field-programmable gate array_section_9

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. Field-programmable gate array_sentence_46

An older study showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations. Field-programmable gate array_sentence_47

More recently, FPGAs such as the Xilinx Virtex-7 or the Altera Stratix 5 have come to rival corresponding ASIC and ASSP ("Application-specific standard part", such as a standalone USB interface chip) solutions by providing significantly reduced power usage, increased speed, lower materials cost, minimal implementation real-estate, and increased possibilities for re-configuration 'on-the-fly'. Field-programmable gate array_sentence_48

A design that included 6 to 10 ASICs can now be achieved using only one FPGA. Field-programmable gate array_sentence_49

Advantages of FPGAs include the ability to re-program when already deployed (i.e. "in the field") to fix bugs, and often include shorter time to market and lower non-recurring engineering costs. Field-programmable gate array_sentence_50

Vendors can also take a middle road via FPGA prototyping: developing their prototype hardware on FPGAs, but manufacture their final version as an ASIC so that it can no longer be modified after the design has been committed. Field-programmable gate array_sentence_51

This is often also the case with new processor designs. Field-programmable gate array_sentence_52

Trends Field-programmable gate array_section_10

Xilinx claimed that several market and technology dynamics are changing the ASIC/FPGA paradigm as of February 2009: Field-programmable gate array_sentence_53

Field-programmable gate array_unordered_list_3

  • Integrated circuit development costs were rising aggressivelyField-programmable gate array_item_3_13
  • ASIC complexity has lengthened development timeField-programmable gate array_item_3_14
  • R&D resources and headcount were decreasingField-programmable gate array_item_3_15
  • Revenue losses for slow time-to-market were increasingField-programmable gate array_item_3_16
  • Financial constraints in a poor economy were driving low-cost technologies.Field-programmable gate array_item_3_17

These trends make FPGAs a better alternative than ASICs for a larger number of higher-volume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts (see § History). Field-programmable gate array_sentence_54

Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running. Field-programmable gate array_sentence_55

Complex Programmable Logic Devices (CPLD) Field-programmable gate array_section_11

The primary differences between complex programmable logic devices (CPLDs) and FPGAs are architectural. Field-programmable gate array_sentence_56

A CPLD has a comparatively restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. Field-programmable gate array_sentence_57

As a result, CPLDs are less flexible, but have the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. Field-programmable gate array_sentence_58

FPGA architectures, on the other hand, are dominated by interconnect. Field-programmable gate array_sentence_59

This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex electronic design automation (EDA) software. Field-programmable gate array_sentence_60

In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Field-programmable gate array_sentence_61

Typically only FPGAs contain more complex embedded functions such as adders, multipliers, memory, and serializer/deserializers. Field-programmable gate array_sentence_62

Another common distinction is that CPLDs contain embedded flash memory to store their configuration while FPGAs usually require external non-volatile memory (but not always). Field-programmable gate array_sentence_63

When a design requires simple instant-on (logic is already configured at power-up) CPLDs are generally preferred. Field-programmable gate array_sentence_64

For most other applications FPGAs are generally preferred. Field-programmable gate array_sentence_65

Sometimes both CPLDs and FPGAs are used in a single system design. Field-programmable gate array_sentence_66

In those designs, CPLDs generally perform glue logic functions, and are responsible for “booting” the FPGA as well as controlling reset and boot sequence of the complete circuit board. Field-programmable gate array_sentence_67

Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design. Field-programmable gate array_sentence_68

Security considerations Field-programmable gate array_section_12

FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors, concerning hardware security. Field-programmable gate array_sentence_69

FPGAs' flexibility makes malicious modifications during fabrication a lower risk. Field-programmable gate array_sentence_70

Previously, for many FPGAs, the design bitstream was exposed while the FPGA loads it from external memory (typically on every power-on). Field-programmable gate array_sentence_71

All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream encryption and authentication. Field-programmable gate array_sentence_72

For example, Altera and Xilinx offer AES encryption (up to 256-bit) for bitstreams stored in an external flash memory. Field-programmable gate array_sentence_73

FPGAs that store their configuration internally in nonvolatile flash memory, such as Microsemi's ProAsic 3 or Lattice's XP2 programmable devices, do not expose the bitstream and do not need encryption. Field-programmable gate array_sentence_74

In addition, flash memory for a lookup table provides single event upset protection for space applications. Field-programmable gate array_sentence_75

Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as Microsemi. Field-programmable gate array_sentence_76

With its Stratix 10 FPGAs and SoCs, Altera introduced a Secure Device Manager and physically uncloneable functions to provide high levels of protection against physical attacks. Field-programmable gate array_sentence_77

In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that FPGAs can be vulnerable to hostile intent. Field-programmable gate array_sentence_78

They discovered a critical backdoor vulnerability had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and access keys, accessing unencrypted bitstream, modifying low-level silicon features, and extracting configuration data. Field-programmable gate array_sentence_79

Applications Field-programmable gate array_section_13

See also: Hardware acceleration Field-programmable gate array_sentence_80

An FPGA can be used to solve any problem which is computable. Field-programmable gate array_sentence_81

This is trivially proven by the fact that FPGAs can be used to implement a soft microprocessor, such as the Xilinx MicroBlaze or Altera Nios II. Field-programmable gate array_sentence_82

Their advantage lies in that they are significantly faster for some applications because of their parallel nature and optimality in terms of the number of gates used for certain processes. Field-programmable gate array_sentence_83

FPGAs originally began as competitors to CPLDs to implement glue logic for printed circuit boards. Field-programmable gate array_sentence_84

As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full systems on chips (SoCs). Field-programmable gate array_sentence_85

Particularly with the introduction of dedicated multipliers into FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of digital signal processor hardware (DSPs) began to incorporate FPGAs instead. Field-programmable gate array_sentence_86

Another trend in the use of FPGAs is hardware acceleration, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a generic processor. Field-programmable gate array_sentence_87

The search engine Bing is noted for adopting FPGA acceleration for its search algorithm in 2014. Field-programmable gate array_sentence_88

As of 2018, FPGAs are seeing increased use as AI accelerators including Microsoft's so-termed "Project Catapult" and for accelerating artificial neural networks for machine learning applications. Field-programmable gate array_sentence_89

Traditionally, FPGAs have been reserved for specific vertical applications where the volume of production is small. Field-programmable gate array_sentence_90

For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Field-programmable gate array_sentence_91

As of 2017, new cost and performance dynamics have broadened the range of viable applications. Field-programmable gate array_sentence_92

Common applications Field-programmable gate array_section_14

Architecture Field-programmable gate array_section_15

Logic blocks Field-programmable gate array_section_16

Main article: Logic block Field-programmable gate array_sentence_93

The most common FPGA architecture consists of an array of logic blocks, I/O pads, and routing channels. Field-programmable gate array_sentence_94

Generally, all the routing channels have the same width (number of wires). Field-programmable gate array_sentence_95

Multiple I/O pads may fit into the height of one row or the width of one column in the array. Field-programmable gate array_sentence_96

An application circuit must be mapped into an FPGA with adequate resources. Field-programmable gate array_sentence_97

While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. Field-programmable gate array_sentence_98

For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Field-programmable gate array_sentence_99

Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of lookup tables (LUTs) and I/Os can be routed. Field-programmable gate array_sentence_100

This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. Field-programmable gate array_sentence_101

As of 2018, network-on-chip architectures for routing and interconnection are being developed. Field-programmable gate array_sentence_102

In general, a logic block consists of a few logical cells (called ALM, LE, slice etc.). Field-programmable gate array_sentence_103

A typical cell consists of a 4-input LUT, a full adder (FA) and a D-type flip-flop, as shown above. Field-programmable gate array_sentence_104

The LUTs are in this figure split into two 3-input LUTs. Field-programmable gate array_sentence_105

In normal mode those are combined into a 4-input LUT through the left multiplexer (mux). Field-programmable gate array_sentence_106

In arithmetic mode, their outputs are fed to the adder. Field-programmable gate array_sentence_107

The selection of mode is programmed into the middle MUX. Field-programmable gate array_sentence_108

The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. Field-programmable gate array_sentence_109

In practice, entire or parts of the adder are stored as functions into the LUTs in order to save space. Field-programmable gate array_sentence_110

Hard blocks Field-programmable gate array_section_17

Modern FPGA families expand upon the above capabilities to include higher level functionality fixed in silicon. Field-programmable gate array_sentence_111

Having these common functions embedded in the circuit reduces the area required and gives those functions increased speed compared to building them from logical primitives. Field-programmable gate array_sentence_112

Examples of these include multipliers, generic DSP blocks, embedded processors, high speed I/O logic and embedded memories. Field-programmable gate array_sentence_113

Higher-end FPGAs can contain high speed multi-gigabit transceivers and hard IP cores such as processor cores, Ethernet medium access control units, PCI/PCI Express controllers, and external memory controllers. Field-programmable gate array_sentence_114

These cores exist alongside the programmable fabric, but they are built out of transistors instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. Field-programmable gate array_sentence_115

The multi-gigabit transceivers also contain high performance analog input and output circuitry along with high-speed serializers and deserializers, components which cannot be built out of LUTs. Field-programmable gate array_sentence_116

Higher-level physical layer (PHY) functionality such as line coding may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA. Field-programmable gate array_sentence_117

Clocking Field-programmable gate array_section_18

Most of the circuitry built inside of an FPGA is synchronous circuitry that requires a clock signal. Field-programmable gate array_sentence_118

FPGAs contain dedicated global and regional routing networks for clock and reset so they can be delivered with minimal skew. Field-programmable gate array_sentence_119

Also, FPGAs generally contain analog phase-locked loop and/or delay-locked loop components to synthesize new clock frequencies as well as attenuate jitter. Field-programmable gate array_sentence_120

Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate clock domains. Field-programmable gate array_sentence_121

These clock signals can be generated locally by an oscillator or they can be recovered from a high speed serial data stream. Field-programmable gate array_sentence_122

Care must be taken when building clock domain crossing circuitry to avoid metastability. Field-programmable gate array_sentence_123

FPGAs generally contain block RAMs that are capable of working as dual port RAMs with different clocks, aiding in the construction of building FIFOs and dual port buffers that connect differing clock domains. Field-programmable gate array_sentence_124

3D architectures Field-programmable gate array_section_19

To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have introduced 3D or stacked architectures. Field-programmable gate array_sentence_125

Following the introduction of its 28 nm 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies. Field-programmable gate array_sentence_126

Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon interposer – a single piece of silicon that carries passive interconnect. Field-programmable gate array_sentence_127

The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. Field-programmable gate array_sentence_128

An FPGA built in this way is called a heterogeneous FPGA. Field-programmable gate array_sentence_129

Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other die/technologies to the FPGA using Intel's embedded multi-die interconnect bridge (EMIB) technology. Field-programmable gate array_sentence_130

Design and programming Field-programmable gate array_section_20

Further information: Logic synthesis, Verification and validation, and Place and route Field-programmable gate array_sentence_131

To define the behavior of the FPGA, the user provides a design in a hardware description language (HDL) or as a schematic design. Field-programmable gate array_sentence_132

The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. Field-programmable gate array_sentence_133

However, schematic entry can allow for easier visualization of a design and its component modules. Field-programmable gate array_sentence_134

Using an electronic design automation tool, a technology-mapped netlist is generated. Field-programmable gate array_sentence_135

The netlist can then be fit to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. Field-programmable gate array_sentence_136

The user will validate the map, place and route results via timing analysis, simulation, and other verification and validation methodologies. Field-programmable gate array_sentence_137

Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. Field-programmable gate array_sentence_138

This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. Field-programmable gate array_sentence_139

The most common HDLs are VHDL and Verilog as well as extensions such as SystemVerilog. Field-programmable gate array_sentence_140

However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages. Field-programmable gate array_sentence_141

National Instruments' LabVIEW graphical programming language (sometimes referred to as "G") has an FPGA add-in module available to target and program FPGA hardware. Field-programmable gate array_sentence_142

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. Field-programmable gate array_sentence_143

These predefined circuits are commonly called intellectual property (IP) cores, and are available from FPGA vendors and third-party IP suppliers. Field-programmable gate array_sentence_144

They are rarely free, and typically released under proprietary licenses. Field-programmable gate array_sentence_145

Other predefined circuits are available from developer communities such as OpenCores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources. Field-programmable gate array_sentence_146

Such designs are known as "open-source hardware." Field-programmable gate array_sentence_147

In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Field-programmable gate array_sentence_148

Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Field-programmable gate array_sentence_149

Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate-level description where simulation is repeated to confirm the synthesis proceeded without errors. Field-programmable gate array_sentence_150

Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. Field-programmable gate array_sentence_151

More recently, OpenCL (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. Field-programmable gate array_sentence_152

OpenCL allows programmers to develop code in the C programming language and target FPGA functions as OpenCL kernels using OpenCL constructs. Field-programmable gate array_sentence_153

For further information, see high-level synthesis and C to HDL. Field-programmable gate array_sentence_154

Basic process technology types Field-programmable gate array_section_21

Field-programmable gate array_unordered_list_4

  • SRAM – based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS. Currently in use. Notably, flash memory or EEPROM devices may often load contents into internal SRAM that controls routing and logic.Field-programmable gate array_item_4_18
  • Fuse – One-time programmable. Bipolar. Obsolete.Field-programmable gate array_item_4_19
  • Antifuse – One-time programmable. CMOS.Field-programmable gate array_item_4_20
  • PROM – Programmable Read-Only Memory technology. One-time programmable because of plastic packaging. Obsolete.Field-programmable gate array_item_4_21
  • EPROM – Erasable Programmable Read-Only Memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.Field-programmable gate array_item_4_22
  • EEPROM – Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS.Field-programmable gate array_item_4_23
  • Flash – Flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.Field-programmable gate array_item_4_24

Major manufacturers Field-programmable gate array_section_22

In 2016, long-time industry rivals Xilinx (now AMD) and Altera (now an Intel subsidiary) were the FPGA market leaders. Field-programmable gate array_sentence_155

At that time, they controlled nearly 90 percent of the market. Field-programmable gate array_sentence_156

Both Xilinx and Altera provide proprietary electronic design automation software for Windows and Linux (ISE/Vivado and Quartus) which enables engineers to design, analyze, simulate, and synthesize (compile) their designs. Field-programmable gate array_sentence_157

Other manufacturers include: Field-programmable gate array_sentence_158

Field-programmable gate array_unordered_list_5

  • Microchip:Field-programmable gate array_item_5_25
    • Microsemi (previously Actel), producing antifuse, flash-based, mixed-signal FPGAs; acquired by Microchip in 2018Field-programmable gate array_item_5_26
    • Atmel, a second source of some Altera-compatible devices; also FPSLIC mentioned above; acquired by Microchip in 2016Field-programmable gate array_item_5_27
  • Lattice Semiconductor, which manufactures low-power SRAM-based FPGAs featuring integrated configuration flash, instant-on and live reconfigurationField-programmable gate array_item_5_28
    • SiliconBlue Technologies, which provides extremely low power SRAM-based FPGAs with optional integrated nonvolatile configuration memory; acquired by Lattice in 2011Field-programmable gate array_item_5_29
  • QuickLogic, which manufactures Ultra Low Power Sensor Hubs, extremely low powered, low density SRAM-based FPGAs, with display bridges MIPI & RGB inputs, MIPI, RGB and LVDS outputsField-programmable gate array_item_5_30
  • Achronix, manufacturing SRAM based FPGAS with 1.5 GHz fabric speedField-programmable gate array_item_5_31

In March 2010, Tabula announced their FPGA technology that uses time-multiplexed logic and interconnect that claims potential cost savings for high-density applications. Field-programmable gate array_sentence_159

On March 24, 2015, Tabula officially shut down. Field-programmable gate array_sentence_160

On June 1, 2015, Intel announced it would acquire Altera for approximately $16.7 billion and completed the acquisition on December 30, 2015. Field-programmable gate array_sentence_161

On October 27, 2020, AMD announced it would acquire Xilinx. Field-programmable gate array_sentence_162

See also Field-programmable gate array_section_23

Field-programmable gate array_unordered_list_6

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