Word (computer architecture)

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In computing, a word is the natural unit of data used by a particular processor design. Word (computer architecture)_sentence_0

A word is a fixed-sized piece of data handled as a unit by the instruction set or the hardware of the processor. Word (computer architecture)_sentence_1

The number of bits in a word (the word size, word width, or word length) is an important characteristic of any specific processor design or computer architecture. Word (computer architecture)_sentence_2

The size of a word is reflected in many aspects of a computer's structure and operation; the majority of the registers in a processor are usually word sized and the largest piece of data that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures. Word (computer architecture)_sentence_3

The largest possible address size, used to designate a location in memory, is typically a hardware word (here, "hardware word" means the full-sized natural word of the processor, as opposed to any other definition used). Word (computer architecture)_sentence_4

Several of the earliest computers (and a few modern as well) used binary-coded decimal rather than plain binary, typically having a word size of 10 or 12 decimal digits, and some early decimal computers had no fixed word length at all. Word (computer architecture)_sentence_5

Early binary systems tended to use word lengths that were some multiple of 6-bits, with the 36-bit word being especially common on mainframe computers. Word (computer architecture)_sentence_6

The introduction of ASCII led to the move to systems with word lengths that were a multiple of 8-bits, with 16-bit machines being popular in the 1970s before the move to modern processors with 32 or 64 bits. Word (computer architecture)_sentence_7

Special-purpose designs like digital signal processors, may have any word length from 4 to 80 bits. Word (computer architecture)_sentence_8

The size of a word can sometimes differ from the expected due to backward compatibility with earlier computers. Word (computer architecture)_sentence_9

If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see Size families below). Word (computer architecture)_sentence_10

Uses of words Word (computer architecture)_section_0

Depending on how a computer is organized, word-size units may be used for: Word (computer architecture)_sentence_11

Word (computer architecture)_description_list_0

  • Fixed-point numbers: Holders for fixed point, usually integer, numerical values may be available in one or in several different sizes, but one of the sizes available will almost always be the word. The other sizes, if any, are likely to be multiples or fractions of the word size. The smaller sizes are normally used only for efficient use of memory; when loaded into the processor, their values usually go into a larger, word sized holder.Word (computer architecture)_item_0_0
  • Floating-point numbers: Holders for floating point numerical values are typically either a word or a multiple of a word.Word (computer architecture)_item_0_1
  • Addresses: Holders for memory addresses must be of a size capable of expressing the needed range of values but not be excessively large, so often the size used is the word though it can also be a multiple or fraction of the word size.Word (computer architecture)_item_0_2
  • Registers: Processor registers are designed with a size appropriate for the type of data they hold, e.g. integers, floating-point numbers, or addresses. Many computer architectures use general-purpose registers that are capable of storing data in multiple representations.Word (computer architecture)_item_0_3
  • Memory–processor transfer: When the processor reads from the memory subsystem into a register or writes a register's value to memory, the amount of data transferred is often a word. Historically, this amount of bits which could be transferred in one cycle was also called a catena in some environments (such as the Bull GAMMA 60 []). In simple memory subsystems, the word is transferred over the memory data bus, which typically has a width of a word or half-word. In memory subsystems that use caches, the word-sized transfer is the one between the processor and the first level of cache; at lower levels of the memory hierarchy larger transfers (which are a multiple of the word size) are normally used.Word (computer architecture)_item_0_4
  • Unit of address resolution: In a given architecture, successive address values designate successive units of memory; this unit is the unit of address resolution. In most computers, the unit is either a character (e.g. a byte) or a word. (A few computers have used bit resolution.) If the unit is a word, then a larger amount of memory can be accessed using an address of a given size at the cost of added complexity to access individual characters. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation).Word (computer architecture)_item_0_5
  • Instructions: Machine instructions are normally the size of the architecture's word, such as in RISC architectures, or a multiple of the "char" size that is a fraction of it. This is a natural choice since instructions and data usually share the same memory subsystem. In Harvard architectures the word sizes of instructions and data need not be related, as instructions and data are stored in different memories; for example, the processor in the 1ESS electronic telephone switch had 37-bit instructions and 23-bit data words.Word (computer architecture)_item_0_6

Word size choice Word (computer architecture)_section_1

When a computer architecture is designed, the choice of a word size is of substantial importance. Word (computer architecture)_sentence_12

There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses. Word (computer architecture)_sentence_13

However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size. Word (computer architecture)_sentence_14

That preferred size becomes the word size of the architecture. Word (computer architecture)_sentence_15

Character size was in the past (pre-variable-sized character encoding) one of the influences on unit of address resolution and the choice of word size. Word (computer architecture)_sentence_16

Before the mid-1960s, characters were most often stored in six bits; this allowed no more than 64 characters, so the alphabet was limited to upper case. Word (computer architecture)_sentence_17

Since it is efficient in time and space to have the word size be a multiple of the character size, word sizes in this period were usually multiples of 6 bits (in binary machines). Word (computer architecture)_sentence_18

A common choice then was the 36-bit word, which is also a good size for the numeric properties of a floating point format. Word (computer architecture)_sentence_19

After the introduction of the IBM System/360 design, which used eight-bit characters and supported lower-case letters, the standard size of a character (or more accurately, a byte) became eight bits. Word (computer architecture)_sentence_20

Word sizes thereafter were naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used. Word (computer architecture)_sentence_21

Variable word architectures Word (computer architecture)_section_2

Early machine designs included some that used what is often termed a variable word length. Word (computer architecture)_sentence_22

In this type of organization, a numeric operand had no fixed length but rather its end was detected when a character with a special marking, often called word mark, was encountered. Word (computer architecture)_sentence_23

Such machines often used binary-coded decimal for numbers. Word (computer architecture)_sentence_24

This class of machines included the IBM 702, IBM 705, IBM 7080, IBM 7010, UNIVAC 1050, IBM 1401, and IBM 1620. Word (computer architecture)_sentence_25

Most of these machines work on one unit of memory at a time and since each instruction or datum is several units long, each instruction takes several cycles just to access memory. Word (computer architecture)_sentence_26

These machines are often quite slow because of this. Word (computer architecture)_sentence_27

For example, instruction fetches on an IBM 1620 Model I take 8 cycles just to read the 12 digits of the instruction (the Model II reduced this to 6 cycles, or 4 cycles if the instruction did not need both address fields). Word (computer architecture)_sentence_28

Instruction execution took a completely variable number of cycles, depending on the size of the operands. Word (computer architecture)_sentence_29

Word and byte addressing Word (computer architecture)_section_3

The memory model of an architecture is strongly influenced by the word size. Word (computer architecture)_sentence_30

In particular, the resolution of a memory address, that is, the smallest unit that can be designated by an address, has often been chosen to be the word. Word (computer architecture)_sentence_31

In this approach, the word-addressable machine approach, address values which differ by one designate adjacent memory words. Word (computer architecture)_sentence_32

This is natural in machines which deal almost always in word (or multiple-word) units, and has the advantage of allowing instructions to use minimally sized fields to contain addresses, which can permit a smaller instruction size or a larger variety of instructions. Word (computer architecture)_sentence_33

When byte processing is to be a significant part of the workload, it is usually more advantageous to use the byte, rather than the word, as the unit of address resolution. Word (computer architecture)_sentence_34

Address values which differ by one designate adjacent bytes in memory. Word (computer architecture)_sentence_35

This allows an arbitrary character within a character string to be addressed straightforwardly. Word (computer architecture)_sentence_36

A word can still be addressed, but the address to be used requires a few more bits than the word-resolution alternative. Word (computer architecture)_sentence_37

The word size needs to be an integer multiple of the character size in this organization. Word (computer architecture)_sentence_38

This addressing approach was used in the IBM 360, and has been the most common approach in machines designed since then. Word (computer architecture)_sentence_39

In a byte-oriented (byte-addressable) machine, moving a single byte from one arbitrary location to another is typically: Word (computer architecture)_sentence_40

Word (computer architecture)_ordered_list_1

  1. LOAD the source byteWord (computer architecture)_item_1_7
  2. STORE the result back in the target byteWord (computer architecture)_item_1_8

Individual bytes can be accessed on a word-oriented machine in one of two ways. Word (computer architecture)_sentence_41

Bytes can be manipulated by a combination of shift and mask operations in registers. Word (computer architecture)_sentence_42

Moving a single byte from one arbitrary location to another may require the equivalent of the following: Word (computer architecture)_sentence_43

Word (computer architecture)_ordered_list_2

  1. LOAD the word containing the source byteWord (computer architecture)_item_2_9
  2. SHIFT the source word to align the desired byte to the correct position in the target wordWord (computer architecture)_item_2_10
  3. AND the source word with a mask to zero out all but the desired bitsWord (computer architecture)_item_2_11
  4. LOAD the word containing the target byteWord (computer architecture)_item_2_12
  5. AND the target word with a mask to zero out the target byteWord (computer architecture)_item_2_13
  6. OR the registers containing the source and target words to insert the source byteWord (computer architecture)_item_2_14
  7. STORE the result back in the target locationWord (computer architecture)_item_2_15

Alternatively many word-oriented machines implement byte operations with instructions using special byte pointers in registers or memory. Word (computer architecture)_sentence_44

For example, the PDP-10 byte pointer contained the size of the byte in bits (allowing different-sized bytes to be accessed), the bit position of the byte within the word, and the word address of the data. Word (computer architecture)_sentence_45

Instructions could automatically adjust the pointer to the next byte on, for example, load and deposit (store) operations. Word (computer architecture)_sentence_46

Powers of two Word (computer architecture)_section_4

Different amounts of memory are used to store data values with different degrees of precision. Word (computer architecture)_sentence_47

The commonly used sizes are usually a power of two multiple of the unit of address resolution (byte or word). Word (computer architecture)_sentence_48

Converting the index of an item in an array into the address of the item then requires only a shift operation rather than a multiplication. Word (computer architecture)_sentence_49

In some cases this relationship can also avoid the use of division operations. Word (computer architecture)_sentence_50

As a result, most modern computer designs have word sizes (and other operand sizes) that are a power of two times the size of a byte. Word (computer architecture)_sentence_51

Size families Word (computer architecture)_section_5

As computer designs have grown more complex, the central importance of a single word size to an architecture has decreased. Word (computer architecture)_sentence_52

Although more capable hardware can use a wider variety of sizes of data, market forces exert pressure to maintain backward compatibility while extending processor capability. Word (computer architecture)_sentence_53

As a result, what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design. Word (computer architecture)_sentence_54

The original word size remains available in future designs, forming the basis of a size family. Word (computer architecture)_sentence_55

In the mid-1970s, DEC designed the VAX to be a 32-bit successor of the 16-bit PDP-11. Word (computer architecture)_sentence_56

They used word for a 16-bit quantity, while longword referred to a 32-bit quantity. Word (computer architecture)_sentence_57

This was in contrast to earlier machines, where the natural unit of addressing memory would be called a word, while a quantity that is one half a word would be called a halfword. Word (computer architecture)_sentence_58

In fitting with this scheme, a VAX quadword is 64 bits. Word (computer architecture)_sentence_59

They continued this word/longword/quadword terminology with the 64-bit Alpha. Word (computer architecture)_sentence_60

Another example is the x86 family, of which processors of three different word lengths (16-bit, later 32- and 64-bit) have been released, while word continues to designate a 16-bit quantity. Word (computer architecture)_sentence_61

As software is routinely ported from one word-length to the next, some APIs and documentation define or refer to an older (and thus shorter) word-length than the full word length on the CPU that software may be compiled for. Word (computer architecture)_sentence_62

Also, similar to how bytes are used for small numbers in many programs, a shorter word (16 or 32 bits) may be used in contexts where the range of a wider word is not needed (especially where this can save considerable stack space or cache memory space). Word (computer architecture)_sentence_63

For example, Microsoft's Windows API maintains the programming language definition of WORD as 16 bits, despite the fact that the API may be used on a 32- or 64-bit x86 processor, where the standard word size would be 32 or 64 bits, respectively. Word (computer architecture)_sentence_64

Data structures containing such different sized words refer to them as WORD (16 bits/2 bytes), DWORD (32 bits/4 bytes) and QWORD (64 bits/8 bytes) respectively. Word (computer architecture)_sentence_65

A similar phenomenon has developed in Intel's x86 assembly language – because of the support for various sizes (and backward compatibility) in the instruction set, some instruction mnemonics carry "d" or "q" identifiers denoting "double-", "quad-" or "double-quad-", which are in terms of the architecture's original 16-bit word size. Word (computer architecture)_sentence_66

In general, new processors must use the same data word lengths and virtual address widths as an older processor to have binary compatibility with that older processor. Word (computer architecture)_sentence_67

Often carefully written source code – written with source code compatibility and software portability in mind – can be recompiled to run on a variety of processors, even ones with different data word lengths or different address widths or both. Word (computer architecture)_sentence_68

Table of word sizes Word (computer architecture)_section_6

Word (computer architecture)_table_general_0

key: bit: bits, d: decimal digits, w: word size of architecture, n: variable sizeWord (computer architecture)_header_cell_0_0_0
YearWord (computer architecture)_header_cell_0_1_0 Computer
architectureWord (computer architecture)_header_cell_0_1_1
Word size wWord (computer architecture)_header_cell_0_1_2 Integer
sizesWord (computer architecture)_header_cell_0_1_3
sizesWord (computer architecture)_header_cell_0_1_4
sizesWord (computer architecture)_header_cell_0_1_5
Unit of address

resolutionWord (computer architecture)_header_cell_0_1_6

Char sizeWord (computer architecture)_header_cell_0_1_7
1837Word (computer architecture)_cell_0_2_0 Babbage

Analytical engineWord (computer architecture)_cell_0_2_1

50 dWord (computer architecture)_cell_0_2_2 wWord (computer architecture)_cell_0_2_3 Word (computer architecture)_cell_0_2_4 Five different cards were used for different functions, exact size of cards not known.Word (computer architecture)_cell_0_2_5 wWord (computer architecture)_cell_0_2_6 Word (computer architecture)_cell_0_2_7
1941Word (computer architecture)_cell_0_3_0 Zuse Z3Word (computer architecture)_cell_0_3_1 22 bitWord (computer architecture)_cell_0_3_2 Word (computer architecture)_cell_0_3_3 wWord (computer architecture)_cell_0_3_4 8 bitWord (computer architecture)_cell_0_3_5 wWord (computer architecture)_cell_0_3_6 Word (computer architecture)_cell_0_3_7
1942Word (computer architecture)_cell_0_4_0 ABCWord (computer architecture)_cell_0_4_1 50 bitWord (computer architecture)_cell_0_4_2 wWord (computer architecture)_cell_0_4_3 Word (computer architecture)_cell_0_4_4 Word (computer architecture)_cell_0_4_5 Word (computer architecture)_cell_0_4_6 Word (computer architecture)_cell_0_4_7
1944Word (computer architecture)_cell_0_5_0 Harvard Mark IWord (computer architecture)_cell_0_5_1 23 dWord (computer architecture)_cell_0_5_2 wWord (computer architecture)_cell_0_5_3 Word (computer architecture)_cell_0_5_4 24 bitWord (computer architecture)_cell_0_5_5 Word (computer architecture)_cell_0_5_6 Word (computer architecture)_cell_0_5_7

(1948) {1953}Word (computer architecture)_cell_0_6_0


(w/Panel #16) {w/Panel #26}Word (computer architecture)_cell_0_6_1

10 dWord (computer architecture)_cell_0_6_2 w, 2w

(w) {w}Word (computer architecture)_cell_0_6_3

Word (computer architecture)_cell_0_6_4

(2 d, 4 d, 6 d, 8 d) {2 d, 4 d, 6 d, 8 d}Word (computer architecture)_cell_0_6_5

— {w}Word (computer architecture)_cell_0_6_6

Word (computer architecture)_cell_0_6_7
1948Word (computer architecture)_cell_0_7_0 Manchester BabyWord (computer architecture)_cell_0_7_1 32 bitWord (computer architecture)_cell_0_7_2 wWord (computer architecture)_cell_0_7_3 Word (computer architecture)_cell_0_7_4 wWord (computer architecture)_cell_0_7_5 wWord (computer architecture)_cell_0_7_6 Word (computer architecture)_cell_0_7_7
1951Word (computer architecture)_cell_0_8_0 UNIVAC IWord (computer architecture)_cell_0_8_1 12 dWord (computer architecture)_cell_0_8_2 wWord (computer architecture)_cell_0_8_3 Word (computer architecture)_cell_0_8_4 ​⁄2wWord (computer architecture)_cell_0_8_5 wWord (computer architecture)_cell_0_8_6 1 dWord (computer architecture)_cell_0_8_7
1952Word (computer architecture)_cell_0_9_0 IAS machineWord (computer architecture)_cell_0_9_1 40 bitWord (computer architecture)_cell_0_9_2 wWord (computer architecture)_cell_0_9_3 Word (computer architecture)_cell_0_9_4 ​⁄2wWord (computer architecture)_cell_0_9_5 wWord (computer architecture)_cell_0_9_6 5 bitWord (computer architecture)_cell_0_9_7
1952Word (computer architecture)_cell_0_10_0 Fast Universal Digital Computer M-2Word (computer architecture)_cell_0_10_1 34 bitWord (computer architecture)_cell_0_10_2 w?Word (computer architecture)_cell_0_10_3 wWord (computer architecture)_cell_0_10_4 34 bit = 4 bit opcode plus 3×10 bit addressWord (computer architecture)_cell_0_10_5 10 bitWord (computer architecture)_cell_0_10_6 Word (computer architecture)_cell_0_10_7
1952Word (computer architecture)_cell_0_11_0 IBM 701Word (computer architecture)_cell_0_11_1 36 bitWord (computer architecture)_cell_0_11_2 ​⁄2w, wWord (computer architecture)_cell_0_11_3 Word (computer architecture)_cell_0_11_4 ​⁄2wWord (computer architecture)_cell_0_11_5 ​⁄2w, wWord (computer architecture)_cell_0_11_6 6 bitWord (computer architecture)_cell_0_11_7
1952Word (computer architecture)_cell_0_12_0 UNIVAC 60Word (computer architecture)_cell_0_12_1 n dWord (computer architecture)_cell_0_12_2 1 d, ... 10 dWord (computer architecture)_cell_0_12_3 Word (computer architecture)_cell_0_12_4 Word (computer architecture)_cell_0_12_5 Word (computer architecture)_cell_0_12_6 2 d, 3 dWord (computer architecture)_cell_0_12_7
1952Word (computer architecture)_cell_0_13_0 ARRA IWord (computer architecture)_cell_0_13_1 30 bitWord (computer architecture)_cell_0_13_2 wWord (computer architecture)_cell_0_13_3 Word (computer architecture)_cell_0_13_4 wWord (computer architecture)_cell_0_13_5 wWord (computer architecture)_cell_0_13_6 5 bitWord (computer architecture)_cell_0_13_7
1953Word (computer architecture)_cell_0_14_0 IBM 702Word (computer architecture)_cell_0_14_1 n dWord (computer architecture)_cell_0_14_2 0 d, ... 511 dWord (computer architecture)_cell_0_14_3 Word (computer architecture)_cell_0_14_4 5 dWord (computer architecture)_cell_0_14_5 dWord (computer architecture)_cell_0_14_6 1 dWord (computer architecture)_cell_0_14_7
1953Word (computer architecture)_cell_0_15_0 UNIVAC 120Word (computer architecture)_cell_0_15_1 n dWord (computer architecture)_cell_0_15_2 1 d, ... 10 dWord (computer architecture)_cell_0_15_3 Word (computer architecture)_cell_0_15_4 Word (computer architecture)_cell_0_15_5 Word (computer architecture)_cell_0_15_6 2 d, 3 dWord (computer architecture)_cell_0_15_7
1953Word (computer architecture)_cell_0_16_0 ARRA IIWord (computer architecture)_cell_0_16_1 30 bitWord (computer architecture)_cell_0_16_2 wWord (computer architecture)_cell_0_16_3 2wWord (computer architecture)_cell_0_16_4 ​⁄2wWord (computer architecture)_cell_0_16_5 wWord (computer architecture)_cell_0_16_6 5 bitWord (computer architecture)_cell_0_16_7

(1955)Word (computer architecture)_cell_0_17_0

IBM 650

(w/IBM 653)Word (computer architecture)_cell_0_17_1

10 dWord (computer architecture)_cell_0_17_2 wWord (computer architecture)_cell_0_17_3

(w)Word (computer architecture)_cell_0_17_4

wWord (computer architecture)_cell_0_17_5 wWord (computer architecture)_cell_0_17_6 2 dWord (computer architecture)_cell_0_17_7
1954Word (computer architecture)_cell_0_18_0 IBM 704Word (computer architecture)_cell_0_18_1 36 bitWord (computer architecture)_cell_0_18_2 wWord (computer architecture)_cell_0_18_3 wWord (computer architecture)_cell_0_18_4 wWord (computer architecture)_cell_0_18_5 wWord (computer architecture)_cell_0_18_6 6 bitWord (computer architecture)_cell_0_18_7
1954Word (computer architecture)_cell_0_19_0 IBM 705Word (computer architecture)_cell_0_19_1 n dWord (computer architecture)_cell_0_19_2 0 d, ... 255 dWord (computer architecture)_cell_0_19_3 Word (computer architecture)_cell_0_19_4 5 dWord (computer architecture)_cell_0_19_5 dWord (computer architecture)_cell_0_19_6 1 dWord (computer architecture)_cell_0_19_7
1954Word (computer architecture)_cell_0_20_0 IBM NORCWord (computer architecture)_cell_0_20_1 16 dWord (computer architecture)_cell_0_20_2 wWord (computer architecture)_cell_0_20_3 w, 2wWord (computer architecture)_cell_0_20_4 wWord (computer architecture)_cell_0_20_5 wWord (computer architecture)_cell_0_20_6 Word (computer architecture)_cell_0_20_7
1956Word (computer architecture)_cell_0_21_0 IBM 305Word (computer architecture)_cell_0_21_1 n dWord (computer architecture)_cell_0_21_2 1 d, ... 100 dWord (computer architecture)_cell_0_21_3 Word (computer architecture)_cell_0_21_4 10 dWord (computer architecture)_cell_0_21_5 dWord (computer architecture)_cell_0_21_6 1 dWord (computer architecture)_cell_0_21_7
1956Word (computer architecture)_cell_0_22_0 ARMACWord (computer architecture)_cell_0_22_1 34 bitWord (computer architecture)_cell_0_22_2 wWord (computer architecture)_cell_0_22_3 wWord (computer architecture)_cell_0_22_4 ​⁄2wWord (computer architecture)_cell_0_22_5 wWord (computer architecture)_cell_0_22_6 5 bit, 6 bitWord (computer architecture)_cell_0_22_7
1957Word (computer architecture)_cell_0_23_0 Autonetics Recomp IWord (computer architecture)_cell_0_23_1 40 bitWord (computer architecture)_cell_0_23_2 w, 79 bit, 8 d, 15 dWord (computer architecture)_cell_0_23_3 Word (computer architecture)_cell_0_23_4 ​⁄2wWord (computer architecture)_cell_0_23_5 ​⁄2w, wWord (computer architecture)_cell_0_23_6 5 bitWord (computer architecture)_cell_0_23_7
1958Word (computer architecture)_cell_0_24_0 UNIVAC IIWord (computer architecture)_cell_0_24_1 12 dWord (computer architecture)_cell_0_24_2 wWord (computer architecture)_cell_0_24_3 Word (computer architecture)_cell_0_24_4 ​⁄2wWord (computer architecture)_cell_0_24_5 wWord (computer architecture)_cell_0_24_6 1 dWord (computer architecture)_cell_0_24_7
1958Word (computer architecture)_cell_0_25_0 SAGEWord (computer architecture)_cell_0_25_1 32 bitWord (computer architecture)_cell_0_25_2 ​⁄2wWord (computer architecture)_cell_0_25_3 Word (computer architecture)_cell_0_25_4 wWord (computer architecture)_cell_0_25_5 wWord (computer architecture)_cell_0_25_6 6 bitWord (computer architecture)_cell_0_25_7
1958Word (computer architecture)_cell_0_26_0 Autonetics Recomp IIWord (computer architecture)_cell_0_26_1 40 bitWord (computer architecture)_cell_0_26_2 w, 79 bit, 8 d, 15 dWord (computer architecture)_cell_0_26_3 2wWord (computer architecture)_cell_0_26_4 ​⁄2wWord (computer architecture)_cell_0_26_5 ​⁄2w, wWord (computer architecture)_cell_0_26_6 5 bitWord (computer architecture)_cell_0_26_7
1958Word (computer architecture)_cell_0_27_0 SetunWord (computer architecture)_cell_0_27_1 trit (~9.5 bit)Word (computer architecture)_cell_0_27_2 up to 6 tryteWord (computer architecture)_cell_0_27_3 Word (computer architecture)_cell_0_27_4 up to 3 trytesWord (computer architecture)_cell_0_27_5 Word (computer architecture)_cell_0_27_6 4 tritWord (computer architecture)_cell_0_27_7
1958Word (computer architecture)_cell_0_28_0 Electrologica X1Word (computer architecture)_cell_0_28_1 27 bitWord (computer architecture)_cell_0_28_2 wWord (computer architecture)_cell_0_28_3 2wWord (computer architecture)_cell_0_28_4 wWord (computer architecture)_cell_0_28_5 wWord (computer architecture)_cell_0_28_6 5 bit, 6 bitWord (computer architecture)_cell_0_28_7
1959Word (computer architecture)_cell_0_29_0 IBM 1401Word (computer architecture)_cell_0_29_1 n dWord (computer architecture)_cell_0_29_2 1 d, ...Word (computer architecture)_cell_0_29_3 Word (computer architecture)_cell_0_29_4 1 d, 2 d, 4 d, 5 d, 7 d, 8 dWord (computer architecture)_cell_0_29_5 dWord (computer architecture)_cell_0_29_6 1 dWord (computer architecture)_cell_0_29_7

(TBD)Word (computer architecture)_cell_0_30_0

IBM 1620Word (computer architecture)_cell_0_30_1 n dWord (computer architecture)_cell_0_30_2 2 d, ...Word (computer architecture)_cell_0_30_3

(4 d, ... 102 d)Word (computer architecture)_cell_0_30_4

12 dWord (computer architecture)_cell_0_30_5 dWord (computer architecture)_cell_0_30_6 2 dWord (computer architecture)_cell_0_30_7
1960Word (computer architecture)_cell_0_31_0 LARCWord (computer architecture)_cell_0_31_1 12 dWord (computer architecture)_cell_0_31_2 w, 2wWord (computer architecture)_cell_0_31_3 w, 2wWord (computer architecture)_cell_0_31_4 wWord (computer architecture)_cell_0_31_5 wWord (computer architecture)_cell_0_31_6 2 dWord (computer architecture)_cell_0_31_7
1960Word (computer architecture)_cell_0_32_0 CDC 1604Word (computer architecture)_cell_0_32_1 48 bitWord (computer architecture)_cell_0_32_2 wWord (computer architecture)_cell_0_32_3 wWord (computer architecture)_cell_0_32_4 ​⁄2wWord (computer architecture)_cell_0_32_5 wWord (computer architecture)_cell_0_32_6 6 bitWord (computer architecture)_cell_0_32_7
1960Word (computer architecture)_cell_0_33_0 IBM 1410Word (computer architecture)_cell_0_33_1 n dWord (computer architecture)_cell_0_33_2 1 d, ...Word (computer architecture)_cell_0_33_3 Word (computer architecture)_cell_0_33_4 1 d, 2 d, 6 d, 7 d, 11 d, 12 dWord (computer architecture)_cell_0_33_5 dWord (computer architecture)_cell_0_33_6 1 dWord (computer architecture)_cell_0_33_7
1960Word (computer architecture)_cell_0_34_0 IBM 7070Word (computer architecture)_cell_0_34_1 10 dWord (computer architecture)_cell_0_34_2 wWord (computer architecture)_cell_0_34_3 wWord (computer architecture)_cell_0_34_4 wWord (computer architecture)_cell_0_34_5 w, dWord (computer architecture)_cell_0_34_6 2 dWord (computer architecture)_cell_0_34_7
1960Word (computer architecture)_cell_0_35_0 PDP-1Word (computer architecture)_cell_0_35_1 18 bitWord (computer architecture)_cell_0_35_2 wWord (computer architecture)_cell_0_35_3 Word (computer architecture)_cell_0_35_4 wWord (computer architecture)_cell_0_35_5 wWord (computer architecture)_cell_0_35_6 6 bitWord (computer architecture)_cell_0_35_7
1960Word (computer architecture)_cell_0_36_0 Elliott 803Word (computer architecture)_cell_0_36_1 39 bitWord (computer architecture)_cell_0_36_2 Word (computer architecture)_cell_0_36_3 Word (computer architecture)_cell_0_36_4 Word (computer architecture)_cell_0_36_5 Word (computer architecture)_cell_0_36_6 Word (computer architecture)_cell_0_36_7
1961Word (computer architecture)_cell_0_37_0 IBM 7030

(Stretch)Word (computer architecture)_cell_0_37_1

64 bitWord (computer architecture)_cell_0_37_2 1 bit, ... 64 bit,

1 d, ... 16 dWord (computer architecture)_cell_0_37_3

wWord (computer architecture)_cell_0_37_4 ​⁄2w, wWord (computer architecture)_cell_0_37_5 b, ​⁄2w, wWord (computer architecture)_cell_0_37_6 1 bit, ... 8 bitWord (computer architecture)_cell_0_37_7
1961Word (computer architecture)_cell_0_38_0 IBM 7080Word (computer architecture)_cell_0_38_1 n dWord (computer architecture)_cell_0_38_2 0 d, ... 255 dWord (computer architecture)_cell_0_38_3 Word (computer architecture)_cell_0_38_4 5 dWord (computer architecture)_cell_0_38_5 dWord (computer architecture)_cell_0_38_6 1 dWord (computer architecture)_cell_0_38_7
1962Word (computer architecture)_cell_0_39_0 GE-6xxWord (computer architecture)_cell_0_39_1 36 bitWord (computer architecture)_cell_0_39_2 w, 2 wWord (computer architecture)_cell_0_39_3 w, 2 w, 80 bitWord (computer architecture)_cell_0_39_4 wWord (computer architecture)_cell_0_39_5 wWord (computer architecture)_cell_0_39_6 6 bit, 9 bitWord (computer architecture)_cell_0_39_7
1962Word (computer architecture)_cell_0_40_0 UNIVAC IIIWord (computer architecture)_cell_0_40_1 25 bitWord (computer architecture)_cell_0_40_2 w, 2w, 3w, 4w, 6 d, 12 dWord (computer architecture)_cell_0_40_3 Word (computer architecture)_cell_0_40_4 wWord (computer architecture)_cell_0_40_5 wWord (computer architecture)_cell_0_40_6 6 bitWord (computer architecture)_cell_0_40_7
1962Word (computer architecture)_cell_0_41_0 Autonetics D-17B

Minuteman I Guidance ComputerWord (computer architecture)_cell_0_41_1

27 bitWord (computer architecture)_cell_0_41_2 11 bit, 24 bitWord (computer architecture)_cell_0_41_3 Word (computer architecture)_cell_0_41_4 24 bitWord (computer architecture)_cell_0_41_5 wWord (computer architecture)_cell_0_41_6 Word (computer architecture)_cell_0_41_7
1962Word (computer architecture)_cell_0_42_0 UNIVAC 1107Word (computer architecture)_cell_0_42_1 36 bitWord (computer architecture)_cell_0_42_2 ​⁄6w, ​⁄3w, ​⁄2w, wWord (computer architecture)_cell_0_42_3 wWord (computer architecture)_cell_0_42_4 wWord (computer architecture)_cell_0_42_5 wWord (computer architecture)_cell_0_42_6 6 bitWord (computer architecture)_cell_0_42_7
1962Word (computer architecture)_cell_0_43_0 IBM 7010Word (computer architecture)_cell_0_43_1 n dWord (computer architecture)_cell_0_43_2 1 d, ...Word (computer architecture)_cell_0_43_3 Word (computer architecture)_cell_0_43_4 1 d, 2 d, 6 d, 7 d, 11 d, 12 dWord (computer architecture)_cell_0_43_5 dWord (computer architecture)_cell_0_43_6 1 dWord (computer architecture)_cell_0_43_7
1962Word (computer architecture)_cell_0_44_0 IBM 7094Word (computer architecture)_cell_0_44_1 36 bitWord (computer architecture)_cell_0_44_2 wWord (computer architecture)_cell_0_44_3 w, 2wWord (computer architecture)_cell_0_44_4 wWord (computer architecture)_cell_0_44_5 wWord (computer architecture)_cell_0_44_6 6 bitWord (computer architecture)_cell_0_44_7
1962Word (computer architecture)_cell_0_45_0 SDS 9 SeriesWord (computer architecture)_cell_0_45_1 24 bitWord (computer architecture)_cell_0_45_2 wWord (computer architecture)_cell_0_45_3 2wWord (computer architecture)_cell_0_45_4 wWord (computer architecture)_cell_0_45_5 wWord (computer architecture)_cell_0_45_6 Word (computer architecture)_cell_0_45_7

(1966)Word (computer architecture)_cell_0_46_0

Apollo Guidance ComputerWord (computer architecture)_cell_0_46_1 15 bitWord (computer architecture)_cell_0_46_2 wWord (computer architecture)_cell_0_46_3 Word (computer architecture)_cell_0_46_4 w, 2wWord (computer architecture)_cell_0_46_5 wWord (computer architecture)_cell_0_46_6 Word (computer architecture)_cell_0_46_7
1963Word (computer architecture)_cell_0_47_0 Saturn Launch Vehicle Digital ComputerWord (computer architecture)_cell_0_47_1 26 bitWord (computer architecture)_cell_0_47_2 wWord (computer architecture)_cell_0_47_3 Word (computer architecture)_cell_0_47_4 13 bitWord (computer architecture)_cell_0_47_5 wWord (computer architecture)_cell_0_47_6 Word (computer architecture)_cell_0_47_7
1964/1966Word (computer architecture)_cell_0_48_0 PDP-6/PDP-10Word (computer architecture)_cell_0_48_1 36 bitWord (computer architecture)_cell_0_48_2 wWord (computer architecture)_cell_0_48_3 w, 2 wWord (computer architecture)_cell_0_48_4 wWord (computer architecture)_cell_0_48_5 wWord (computer architecture)_cell_0_48_6 6 bit, 9 bit (typical)Word (computer architecture)_cell_0_48_7
1964Word (computer architecture)_cell_0_49_0 Titan Word (computer architecture)_cell_0_49_1 48 bitWord (computer architecture)_cell_0_49_2 wWord (computer architecture)_cell_0_49_3 wWord (computer architecture)_cell_0_49_4 wWord (computer architecture)_cell_0_49_5 wWord (computer architecture)_cell_0_49_6 wWord (computer architecture)_cell_0_49_7
1964Word (computer architecture)_cell_0_50_0 CDC 6600Word (computer architecture)_cell_0_50_1 60 bitWord (computer architecture)_cell_0_50_2 wWord (computer architecture)_cell_0_50_3 wWord (computer architecture)_cell_0_50_4 ​⁄4w, ​⁄2wWord (computer architecture)_cell_0_50_5 wWord (computer architecture)_cell_0_50_6 6 bitWord (computer architecture)_cell_0_50_7
1964Word (computer architecture)_cell_0_51_0 Autonetics D-37C

Minuteman II Guidance ComputerWord (computer architecture)_cell_0_51_1

27 bitWord (computer architecture)_cell_0_51_2 11 bit, 24 bitWord (computer architecture)_cell_0_51_3 Word (computer architecture)_cell_0_51_4 24 bitWord (computer architecture)_cell_0_51_5 wWord (computer architecture)_cell_0_51_6 4 bit, 5 bitWord (computer architecture)_cell_0_51_7
1965Word (computer architecture)_cell_0_52_0 Gemini Guidance ComputerWord (computer architecture)_cell_0_52_1 39 bitWord (computer architecture)_cell_0_52_2 26 bitWord (computer architecture)_cell_0_52_3 Word (computer architecture)_cell_0_52_4 13 bitWord (computer architecture)_cell_0_52_5 13 bit, 26Word (computer architecture)_cell_0_52_6 —bitWord (computer architecture)_cell_0_52_7
1965Word (computer architecture)_cell_0_53_0 IBM 360Word (computer architecture)_cell_0_53_1 32 bitWord (computer architecture)_cell_0_53_2 ​⁄2w, w,

1 d, ... 16 dWord (computer architecture)_cell_0_53_3

w, 2wWord (computer architecture)_cell_0_53_4 ​⁄2w, w, 1​⁄2wWord (computer architecture)_cell_0_53_5 8 bitWord (computer architecture)_cell_0_53_6 8 bitWord (computer architecture)_cell_0_53_7
1965Word (computer architecture)_cell_0_54_0 UNIVAC 1108Word (computer architecture)_cell_0_54_1 36 bitWord (computer architecture)_cell_0_54_2 ​⁄6w, ​⁄4w, ​⁄3w, ​⁄2w, w, 2wWord (computer architecture)_cell_0_54_3 w, 2wWord (computer architecture)_cell_0_54_4 wWord (computer architecture)_cell_0_54_5 wWord (computer architecture)_cell_0_54_6 6 bit, 9 bitWord (computer architecture)_cell_0_54_7
1965Word (computer architecture)_cell_0_55_0 PDP-8Word (computer architecture)_cell_0_55_1 12 bitWord (computer architecture)_cell_0_55_2 wWord (computer architecture)_cell_0_55_3 Word (computer architecture)_cell_0_55_4 wWord (computer architecture)_cell_0_55_5 wWord (computer architecture)_cell_0_55_6 8 bitWord (computer architecture)_cell_0_55_7
1965Word (computer architecture)_cell_0_56_0 Electrologica X8Word (computer architecture)_cell_0_56_1 27 bitWord (computer architecture)_cell_0_56_2 wWord (computer architecture)_cell_0_56_3 2wWord (computer architecture)_cell_0_56_4 wWord (computer architecture)_cell_0_56_5 wWord (computer architecture)_cell_0_56_6 6 bit, 7 bitWord (computer architecture)_cell_0_56_7
1966Word (computer architecture)_cell_0_57_0 SDS Sigma 7Word (computer architecture)_cell_0_57_1 32 bitWord (computer architecture)_cell_0_57_2 ​⁄2w, wWord (computer architecture)_cell_0_57_3 w, 2wWord (computer architecture)_cell_0_57_4 wWord (computer architecture)_cell_0_57_5 8 bitWord (computer architecture)_cell_0_57_6 8 bitWord (computer architecture)_cell_0_57_7
1969Word (computer architecture)_cell_0_58_0 Four Phase Systems AL1Word (computer architecture)_cell_0_58_1 8 bitWord (computer architecture)_cell_0_58_2 wWord (computer architecture)_cell_0_58_3 Word (computer architecture)_cell_0_58_4 ?Word (computer architecture)_cell_0_58_5 ?Word (computer architecture)_cell_0_58_6 ?Word (computer architecture)_cell_0_58_7
1970Word (computer architecture)_cell_0_59_0 MP944Word (computer architecture)_cell_0_59_1 20 bitWord (computer architecture)_cell_0_59_2 wWord (computer architecture)_cell_0_59_3 Word (computer architecture)_cell_0_59_4 ?Word (computer architecture)_cell_0_59_5 ?Word (computer architecture)_cell_0_59_6 ?Word (computer architecture)_cell_0_59_7
1970Word (computer architecture)_cell_0_60_0 PDP-11Word (computer architecture)_cell_0_60_1 16 bitWord (computer architecture)_cell_0_60_2 wWord (computer architecture)_cell_0_60_3 2w, 4wWord (computer architecture)_cell_0_60_4 w, 2w, 3wWord (computer architecture)_cell_0_60_5 8 bitWord (computer architecture)_cell_0_60_6 8 bitWord (computer architecture)_cell_0_60_7
1971Word (computer architecture)_cell_0_61_0 TMS1802NCWord (computer architecture)_cell_0_61_1 4 bitWord (computer architecture)_cell_0_61_2 wWord (computer architecture)_cell_0_61_3 Word (computer architecture)_cell_0_61_4 ?Word (computer architecture)_cell_0_61_5 ?Word (computer architecture)_cell_0_61_6 Word (computer architecture)_cell_0_61_7
1971Word (computer architecture)_cell_0_62_0 Intel 4004Word (computer architecture)_cell_0_62_1 4 bitWord (computer architecture)_cell_0_62_2 w, dWord (computer architecture)_cell_0_62_3 Word (computer architecture)_cell_0_62_4 2w, 4wWord (computer architecture)_cell_0_62_5 wWord (computer architecture)_cell_0_62_6 Word (computer architecture)_cell_0_62_7
1972Word (computer architecture)_cell_0_63_0 Intel 8008Word (computer architecture)_cell_0_63_1 8 bitWord (computer architecture)_cell_0_63_2 w, 2 dWord (computer architecture)_cell_0_63_3 Word (computer architecture)_cell_0_63_4 w, 2w, 3wWord (computer architecture)_cell_0_63_5 wWord (computer architecture)_cell_0_63_6 8 bitWord (computer architecture)_cell_0_63_7
1972Word (computer architecture)_cell_0_64_0 Calcomp 900Word (computer architecture)_cell_0_64_1 9 bitWord (computer architecture)_cell_0_64_2 wWord (computer architecture)_cell_0_64_3 Word (computer architecture)_cell_0_64_4 w, 2wWord (computer architecture)_cell_0_64_5 wWord (computer architecture)_cell_0_64_6 8 bitWord (computer architecture)_cell_0_64_7
1974Word (computer architecture)_cell_0_65_0 Intel 8080Word (computer architecture)_cell_0_65_1 8 bitWord (computer architecture)_cell_0_65_2 w, 2w, 2 dWord (computer architecture)_cell_0_65_3 Word (computer architecture)_cell_0_65_4 w, 2w, 3wWord (computer architecture)_cell_0_65_5 wWord (computer architecture)_cell_0_65_6 8 bitWord (computer architecture)_cell_0_65_7
1975Word (computer architecture)_cell_0_66_0 ILLIAC IVWord (computer architecture)_cell_0_66_1 64 bitWord (computer architecture)_cell_0_66_2 wWord (computer architecture)_cell_0_66_3 w, ​⁄2wWord (computer architecture)_cell_0_66_4 wWord (computer architecture)_cell_0_66_5 wWord (computer architecture)_cell_0_66_6 Word (computer architecture)_cell_0_66_7
1975Word (computer architecture)_cell_0_67_0 Motorola 6800Word (computer architecture)_cell_0_67_1 8 bitWord (computer architecture)_cell_0_67_2 w, 2 dWord (computer architecture)_cell_0_67_3 Word (computer architecture)_cell_0_67_4 w, 2w, 3wWord (computer architecture)_cell_0_67_5 wWord (computer architecture)_cell_0_67_6 8 bitWord (computer architecture)_cell_0_67_7
1975Word (computer architecture)_cell_0_68_0 MOS Tech. 6501

MOS Tech. 6502Word (computer architecture)_cell_0_68_1

8 bitWord (computer architecture)_cell_0_68_2 w, 2 dWord (computer architecture)_cell_0_68_3 Word (computer architecture)_cell_0_68_4 w, 2w, 3wWord (computer architecture)_cell_0_68_5 wWord (computer architecture)_cell_0_68_6 8 bitWord (computer architecture)_cell_0_68_7
1976Word (computer architecture)_cell_0_69_0 Cray-1Word (computer architecture)_cell_0_69_1 64 bitWord (computer architecture)_cell_0_69_2 24 bit, wWord (computer architecture)_cell_0_69_3 wWord (computer architecture)_cell_0_69_4 ​⁄4w, ​⁄2wWord (computer architecture)_cell_0_69_5 wWord (computer architecture)_cell_0_69_6 8 bitWord (computer architecture)_cell_0_69_7
1976Word (computer architecture)_cell_0_70_0 Zilog Z80Word (computer architecture)_cell_0_70_1 8 bitWord (computer architecture)_cell_0_70_2 w, 2w, 2 dWord (computer architecture)_cell_0_70_3 Word (computer architecture)_cell_0_70_4 w, 2w, 3w, 4w, 5wWord (computer architecture)_cell_0_70_5 wWord (computer architecture)_cell_0_70_6 8 bitWord (computer architecture)_cell_0_70_7

(1980)Word (computer architecture)_cell_0_71_0

16-bit x86 (Intel 8086)

(w/floating point: Intel 8087)Word (computer architecture)_cell_0_71_1

16 bitWord (computer architecture)_cell_0_71_2 ​⁄2w, w, 2 dWord (computer architecture)_cell_0_71_3

(2w, 4w, 5w, 17 d)Word (computer architecture)_cell_0_71_4

​⁄2w, w, ... 7wWord (computer architecture)_cell_0_71_5 8 bitWord (computer architecture)_cell_0_71_6 8 bitWord (computer architecture)_cell_0_71_7
1978Word (computer architecture)_cell_0_72_0 VAXWord (computer architecture)_cell_0_72_1 32 bitWord (computer architecture)_cell_0_72_2 ​⁄4w, ​⁄2w, w, 1 d, ... 31 d, 1 bit, ... 32 bitWord (computer architecture)_cell_0_72_3 w, 2wWord (computer architecture)_cell_0_72_4 ​⁄4w, ... 14​⁄4wWord (computer architecture)_cell_0_72_5 8 bitWord (computer architecture)_cell_0_72_6 8 bitWord (computer architecture)_cell_0_72_7

(1984)Word (computer architecture)_cell_0_73_0

Motorola 68000 series

(w/floating point)Word (computer architecture)_cell_0_73_1

32 bitWord (computer architecture)_cell_0_73_2 ​⁄4w, ​⁄2w, w, 2 dWord (computer architecture)_cell_0_73_3

(w, 2w, 2​⁄2w)Word (computer architecture)_cell_0_73_4

​⁄2w, w, ... 7​⁄2wWord (computer architecture)_cell_0_73_5 8 bitWord (computer architecture)_cell_0_73_6 8 bitWord (computer architecture)_cell_0_73_7
1985Word (computer architecture)_cell_0_74_0 IA-32 (Intel 80386) (w/floating point)Word (computer architecture)_cell_0_74_1 32 bitWord (computer architecture)_cell_0_74_2 ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_74_3

(w, 2w, 80 bit)Word (computer architecture)_cell_0_74_4

8 bit, ... 120 bit

​⁄4w ... 3​⁄4wWord (computer architecture)_cell_0_74_5

8 bitWord (computer architecture)_cell_0_74_6 8 bitWord (computer architecture)_cell_0_74_7
1985Word (computer architecture)_cell_0_75_0 ARMv1Word (computer architecture)_cell_0_75_1 32 bitWord (computer architecture)_cell_0_75_2 ​⁄4w, wWord (computer architecture)_cell_0_75_3 Word (computer architecture)_cell_0_75_4 wWord (computer architecture)_cell_0_75_5 8 bitWord (computer architecture)_cell_0_75_6 8 bitWord (computer architecture)_cell_0_75_7
1985Word (computer architecture)_cell_0_76_0 MIPSWord (computer architecture)_cell_0_76_1 32 bitWord (computer architecture)_cell_0_76_2 ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_76_3 w, 2wWord (computer architecture)_cell_0_76_4 wWord (computer architecture)_cell_0_76_5 8 bitWord (computer architecture)_cell_0_76_6 8 bitWord (computer architecture)_cell_0_76_7
1991Word (computer architecture)_cell_0_77_0 Cray C90Word (computer architecture)_cell_0_77_1 64 bitWord (computer architecture)_cell_0_77_2 32 bit, wWord (computer architecture)_cell_0_77_3 wWord (computer architecture)_cell_0_77_4 ​⁄4w, ​⁄2w, 48 bitWord (computer architecture)_cell_0_77_5 wWord (computer architecture)_cell_0_77_6 8 bitWord (computer architecture)_cell_0_77_7
1992Word (computer architecture)_cell_0_78_0 AlphaWord (computer architecture)_cell_0_78_1 64 bitWord (computer architecture)_cell_0_78_2 8 bit, ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_78_3 ​⁄2w, wWord (computer architecture)_cell_0_78_4 ​⁄2wWord (computer architecture)_cell_0_78_5 8 bitWord (computer architecture)_cell_0_78_6 8 bitWord (computer architecture)_cell_0_78_7
1992Word (computer architecture)_cell_0_79_0 PowerPCWord (computer architecture)_cell_0_79_1 32 bitWord (computer architecture)_cell_0_79_2 ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_79_3 w, 2wWord (computer architecture)_cell_0_79_4 wWord (computer architecture)_cell_0_79_5 8 bitWord (computer architecture)_cell_0_79_6 8 bitWord (computer architecture)_cell_0_79_7
1996Word (computer architecture)_cell_0_80_0 ARMv4

(w/Thumb)Word (computer architecture)_cell_0_80_1

32 bitWord (computer architecture)_cell_0_80_2 ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_80_3 Word (computer architecture)_cell_0_80_4 w

(​⁄2w, w)Word (computer architecture)_cell_0_80_5

8 bitWord (computer architecture)_cell_0_80_6 8 bitWord (computer architecture)_cell_0_80_7
2000Word (computer architecture)_cell_0_81_0 IBM z/Architecture

(w/vector facility)Word (computer architecture)_cell_0_81_1

64 bitWord (computer architecture)_cell_0_81_2 ​⁄4w, ​⁄2w, w

1 d, ... 31 dWord (computer architecture)_cell_0_81_3

​⁄2w, w, 2wWord (computer architecture)_cell_0_81_4 ​⁄4w, ​⁄2w, ​⁄4wWord (computer architecture)_cell_0_81_5 8 bitWord (computer architecture)_cell_0_81_6 8 bit, UTF-16, UTF-32Word (computer architecture)_cell_0_81_7
2001Word (computer architecture)_cell_0_82_0 IA-64Word (computer architecture)_cell_0_82_1 64 bitWord (computer architecture)_cell_0_82_2 8 bit, ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_82_3 ​⁄2w, wWord (computer architecture)_cell_0_82_4 41 bitWord (computer architecture)_cell_0_82_5 8 bitWord (computer architecture)_cell_0_82_6 8 bitWord (computer architecture)_cell_0_82_7
2001Word (computer architecture)_cell_0_83_0 ARMv6

(w/VFP)Word (computer architecture)_cell_0_83_1

32 bitWord (computer architecture)_cell_0_83_2 8 bit, ​⁄2w, wWord (computer architecture)_cell_0_83_3

(w, 2w)Word (computer architecture)_cell_0_83_4

​⁄2w, wWord (computer architecture)_cell_0_83_5 8 bitWord (computer architecture)_cell_0_83_6 8 bitWord (computer architecture)_cell_0_83_7
2003Word (computer architecture)_cell_0_84_0 x86-64Word (computer architecture)_cell_0_84_1 64 bitWord (computer architecture)_cell_0_84_2 8 bit, ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_84_3 ​⁄2w, w, 80 bitWord (computer architecture)_cell_0_84_4 8 bit, ... 120 bitWord (computer architecture)_cell_0_84_5 8 bitWord (computer architecture)_cell_0_84_6 8 bitWord (computer architecture)_cell_0_84_7
2013Word (computer architecture)_cell_0_85_0 ARMv8-AWord (computer architecture)_cell_0_85_1 64 bitWord (computer architecture)_cell_0_85_2 8 bit, ​⁄4w, ​⁄2w, wWord (computer architecture)_cell_0_85_3 ​⁄2w, wWord (computer architecture)_cell_0_85_4 ​⁄2wWord (computer architecture)_cell_0_85_5 8 bitWord (computer architecture)_cell_0_85_6 8 bitWord (computer architecture)_cell_0_85_7
YearWord (computer architecture)_header_cell_0_86_0 Computer
architectureWord (computer architecture)_header_cell_0_86_1
Word size wWord (computer architecture)_header_cell_0_86_2 Integer
sizesWord (computer architecture)_header_cell_0_86_3
sizesWord (computer architecture)_header_cell_0_86_4
sizesWord (computer architecture)_header_cell_0_86_5
Unit of address

resolutionWord (computer architecture)_header_cell_0_86_6

Char sizeWord (computer architecture)_header_cell_0_86_7
key: bit: bits, d: decimal digits, w: word size of architecture, n: variable sizeWord (computer architecture)_header_cell_0_87_0

See also Word (computer architecture)_section_7

Word (computer architecture)_unordered_list_3

Credits to the contents of this page go to the authors of the corresponding Wikipedia page: en.wikipedia.org/wiki/Word (computer architecture).